Latest research
Hardware-Algorithm Co-design for Iterative Half-Pixel Motion Estimation Using Inter-Level Systolic Array
in Circuits, Systems, and Signal Processing- Rohan Mukherjee
- Baishik Biswas
Article 08 June 2026A scalable architecture for quantum information processors: qubit partitioning, placement, and scheduling for minimized circuit latency
in EPJ Quantum Technology- Zahra Alimohammadi
- Naser Mohammadzadeh
- Hatam Abdoli
The g-extra H-structure diagnosability for assessing structural fault quantity in multiprocessor systems
in The Journal of Supercomputing- Nengjin Zhuo
- Shumin Zhang
- Bo Zhu
Article 12 May 2026Flexible parallel sliding window and data flow methods for deep neural networks on processing-in-memory architectures
in The Journal of Supercomputing- Shirin Ghafouri pourKermani
- Majid Mohammadi
- Mokhtar Mohammadi Ghanatghestani
Article 05 May 2026Euro-Par 2025: Parallel Processing Workshops
Conference proceedings 2026Hybrid deep learning architecture for efficient human activity recognition: a CNN-attention-BiLSTM framework
in CCF Transactions on Pervasive Computing and Interaction- Sudipta Saha
- Purba Mukhopadhyay
- Koushik Majumder
Article 29 April 2026A comprehensive review and multi-parameter analysis of CMOS double-balanced Gilbert cell mixers across technology nodes from 180-22 nm
in Analog Integrated Circuits and Signal Processing- Richa Gupta
- P. Hari Krishna Prasad
Article 24 April 2026A Scalable Parallel Architecture for Fast Walsh Hadamard Transform
in Circuits, Systems, and Signal Processing- Pulak Mazumder
- Kusal Bhattacharyya
- Mrinal Kanti Naskar
Article 21 April 2026Exploiting intra-core heterogeneity for high-performance dense linear algebra on Huawei Ascend 910 NPUs
in CCF Transactions on High Performance Computing- Shina Guo
- Weiguo Gao
- Yuan Tang
Article 21 April 2026Throughput impact of software multithreading for deep-learning inference on the AMD Kria KV260
in Journal of Real-Time Image Processing- Claudino Costa
- José Henrique Brito
Design and FPGA implementation of an area-efficient elliptic curve cryptographic processor
in Telecommunication Systems- Bukke Chandrababu Naik
- B. Naresh Kumar Reddy
Article 18 April 2026A multi-stage convolutional and self-attention architecture for high-precision sign language gesture recognition
in The Journal of Supercomputing- Ahmed Kasapbaşı
- Hüseyin Canbolat
Revisiting the ordering of channel and spatial attention: a comprehensive study on sequential and parallel designs
in Signal, Image and Video Processing- Zhongming Liu
- Bingbing Jiang
Article 15 April 2026STAR: an adaptive thermal-delay-throughput aware routing algorithm for vertically-partially-connected 3D NoC
in The Journal of Supercomputing- Jiahong Ning
- Jingbo Shao
Article 12 April 20263-Tier CFET 6T-SRAM with 2D-TMDs channels for Angstrom technology node
in Scientific Reports- Jonghun Lee
- Junyeol Lee
- Jongwook Jeon
Large processor chip model
in Science China Information Sciences- Kaiyan Chang
- Mingzhi Chen
- Jiacheng Zhao
Article 09 April 2026Efficient neural network acceleration using redundant residue number systems
in The Journal of Supercomputing- Soudabeh Mousavi
- Dara Rahmati
- Jungrae Kim
Article 07 April 2026SaaR: a strategy for energy efficiency in DVFS computing platforms beyond the scaling axiomatic approach
in The Journal of Supercomputing- Tarek Hagras
- Gamal A. El-Sayed
Bicameral+ Cache: re-assessing split vector and scalar cache designs for increased efficiency
in The Journal of Supercomputing- Aitor Echevarría
- Susana Rebolledo
- Peter Hsu
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