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概要
高位合成言語アセンブラを作る。
ソースから、verilogを生成するコンパイラを作る。
生成したverilog
module x(input a, input b, output c, output d);
assign c = a ^ b;
assign d = a | b;
endmodule
module testbench;
reg a, b;
x u(.a(a), .b(b), .c(c), .d(d));
initial
begin
$display("a b c d ");
$monitor("%b %b %b %b ", a, b, c, d);
a = 0; b = 0; #10;
a = 0; b = 1; #10;
a = 1; b = 0; #10;
a = 1; b = 1; #10;
$finish;
end
endmodule
成果物
以上。
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