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The Linux of chips, the open source RISC-V instruction set architecture, has some big-name backers including Intel, AMD and Nvidia. But the software support is still far from mature.
RISC-V International, the organization responsible for defining the instruction set architecture, has laid out a roadmap to boost low-level software to improve its appeal to hardware and software developers.
The chip architecture is free to license, and silicon companies can take the open source design and tweak it to the specific needs. RISC-V is a free alternative to architectures like x86 and ARM, for which customers have to pay licensing fees or royalties. RISC-V is viewed as a hardware equivalent to Linux, which is open source but can be customized to specific needs.
Computers are available with RISC-V chips developed by companies like SiFive. Intel has committed $1 billion to the designing and manufacturing of chips that include RISC-V, ARM and x86, and is partnering with Barcelona Supercomputing Centre to make a RISC-V supercomputing chip.
The RISC-V architecture is modular, with a base architecture design around which different modules can be attached. The RISC-V Foundation is adding new specifications to its architecture and is also considering standardizing custom specifications developed by member companies. The goal is to reduce fragmentation, a problem that sealed the fate of the MIPS architecture.
“RISC-V is ratifying four specifications that are coming this quarter,” said Mark Himelstein, the chief technology officer at RISC-V International.
The most important specification is RISC-V for SBI, which is more of a hypervisor layer that helps the operating system kernel talk to the hardware platform. It is the interface between operating systems, hypervisors and firmware. RISC-V specification for SBI architects a firmware layer between the hardware platform and the operating system kernel using an application binary interface in supervisor mode (S-mode or VS-mode).
The spec is machine-level code to access various configuration information and to do non-frequent activities in systems.
“Originally this was done as an abstraction technique so that it wasn’t in 1,500 places. It’s also now become very important for security so that only this layer actually accesses it,” Himelstein said.
RISC-V has done a proof of concept for this, run it on simulators, and is enthusiastic about this, Himelstein said.
The second spec that will be ratified includes the RISC-V Unified Extensible Firmware Interface (UEFI) Protocols, which is the boot interface, much like the ones in existing Linux and Windows systems.
“There is an upstream project and we worked very closely with them to get our changes vetted, but then they blessed it. The board ratified that one as well. It’s one of those little pieces that the ecosystem needs,” Himelstein said.
This year RISC-V International also plans to introduce “profiles,” which are sets of standardized instructions for different applications. Himelstein hopes profiles will reduce the software effort by forcing hardware to have a constrained set of things that work together.
There’s a list of instructions in the profiles under names such as RVA20, which are application layers. That goes to the compiler, it gets a flag and marks the binary. The operating system can go and verify that it can run that binary or respond back that it doesn’t support the profile and cannot run that binary.
“It’s a way to make sure that stuff is together. The distros then don’t have to go ahead and handle particular choices of every single vendor. The vendors like it because we, the community, bear the brunt of moving the software ecosystem along to support those sorts of things,” Himelstein said.
Companies such as Google and Alibaba are also backing RISC-V. Companies in Russia and China — which have limited access to the most advanced x86 chips — are also developing chips based on RISC-V architecture.
