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⇱ Quiz about Logic Gate in Digital logic PYQ QUIZ GATE CS

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Question 1

Which one of the following is NOT logically equivalent to ¬∃x(∀y(α)∧∀z(β))?

  • ∀x(∃z(¬β)->∀y(α))

  • ∀x(∀z(β)->∃y(¬α))

  • ∀x(∀y(α)->∃z(¬β))

  • ∀x(∃y(¬α)->∃z(¬β))

Question 2

Which one of the following expressions does NOT represent exclusive NOR of x and y?

  • xy+x'y'

  • x⊕y'

  • x'⊕y

  • x'⊕y'

Question 3

Which one of the following circuits is NOT equivalent to a 2-input XNOR (exclusive NOR) gate?

👁 GATECS201113

  • A

  • B

  • C

  • D

Question 4

What is the Boolean expression for the output f of the combinational logic circuit of NOR gates given below? 👁 CSE_201031

  • (Q+R)'

  • (P+Q)'

  • (P+R)

  • (P+Q+R)'

Question 5

The Boolean expression for the output 'f' of the multiplexer shown below is:

👁 2010



  • (P⊕ Q⊕ R)'

  • P⊕ Q⊕ R

  • (P+Q+R)'

  • P+Q+R

Question 6

The minterm expansion of f(P, Q, R) = PQ + QR' + PR' is

  • m2 + m4 + m6 + m7

  • m0 + m1 + m3 + m5

  • m0 + m1 + m6 + m7

  • m2 + m3 + m4 + m5

Question 7

What is the minimum number of gates required to implement the Boolean function (AB+C) if we have to use only 2-input NOR gates?

  • 2

  • 3

  • 4

  • 5

Question 8

A 4-bit carry lookahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic.

  • 4 time units

  • 6 time units

  • 10 time units

  • 12 time units

Question 9

A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit ripple-carry binary adder is implemented by using full adders. The total propagation time of this 4-bit binary adder in microseconds is

  • 12 microsecond

  • 19.2 microseconds

  • 21.9 microseconds

  • 17.6 microseconds

Question 10

Consider the following logic circuit whose inputs and function and output is f.

👁 logic-gates
Figure


Given that 

f1(dx, y, z) = ∑(0, 1, 3, 5),
f2(dx, y, z) = ∑(6, 7) and
f(dx, y, z) = ∑(1, 4, 5),

f3 is :

  • ∑(1, 4, 5)

  • ∑(6, 7)

  • ∑(0, 1, 3, 5)

  • None of these

There are 19 questions to complete.

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