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Question 1
Which of the following DMA transfer modes and interrupt handling mechanisms will enable the highest I/O band-width?
Transparent DMA and Polling interrupts
Cycle-stealing and Vectored interrupts
Block transfer and Vectored interrupts
Block transfer and Polling interrupts
Question 2
On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.
Initialize the address register
Initialize the count to 500
LOOP: Load a byte from device
Store in memory at address given by address register
Increment the address register
Decrement the count
If count != 0 go to LOOP
Assume that each statement in this program is equivalent to machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute. The designer of the system also has an alternate approach of using DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?
3.4
4.4
5.1
6.7
Question 3
A micro program control unit is required to generate a total of 25 control signals. Assume that during any microinstruction , at most two control signals are active. Minimum number of bits required in the control word to generate the required control signals will be
2
2.5
10
12
Question 4
Micro program is
the name of a source program in micro computers
set of micro instructions that defines the individual operations in response to a machine-language instruction
a primitive form of macros used in assembly language programming
a very small segment of machine code
Question 5
A computer uses ternary system instead of the traditional binary system. An n bit string in the binary system will occupy
3 + n ternary digits
2n / 3 ternary digits
n(log23) ternary digits
n(log32 ) ternary digits
Question 6
In comparison with static RAM memory, the dynamic Ram memory has
lower bit density and higher power consumption
higher bit density and higher power consumption
lower bit density and lower power consumption
higher bit density and lower power consumption
Question 7
The microinstructions stored in the control memory of a processor have a width of 26 bits. Each microinstruction is divided into three fields. a micro operation field of 13 bits, a next address field (X), and a MUX select field (Y). There are 8 status bits in the inputs of the MUX. How many bits are there in the X and Y fields, and what is the size of the control memory in number of words
10, 3, 1024
8, 5, 256
5, 8, 2048
10, 3, 512
Question 8
Which of the following statements about synchronous and asynchronous I/O is NOT true?
An ISR is invoked on completion of I/O in synchronous I/O but not in asynchronous I/O
In both synchronous and asynchronous I/O, an ISR (Interrupt Service Routine) is invoked after completion of the I/O
A process making a synchronous I/O call waits until I/O is complete, but a process making an asynchronous I/O call does not wait for completion of the I/O
In the case of synchronous I/O, the process waiting for the completion of I/O is woken up by the ISR that is invoked after the completion of I/O
Question 9
In DMA transfer scheme, the transfer scheme other than burst mode is
cycle technique
stealing technique
cycle stealing technique
cycle bypass technique
Question 10
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a 4 x 6 array, where each chip is 8K x 4 bits ?
13
15
16
17
There are 23 questions to complete.
