Consider the data given in Q50 question. If all the flip-flops were reset to 0 at power on, what is the total number of distinct outputs (states) represented by PQR generated by the counter?

Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration. 

If at some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?

The minimum number of D flip-flops needed to design a mod-258 counter is.

In the sequential circuit shown below,if the initial value of the output Q1Q0 is 00,what are the next four values of Q1Q0? 

Given the following state table of an FSM with two states A and B, one input and one output:

If the initial state is A=0, B=0, what is the minimum length of an input string which will take the machine to the state A=0, B=1 with Output = 1?

Consider the following circuit. 👁 Image

The flip-flops are positive edge triggered D FFs. Each state is designated as a two bit string Q₀Q₁. Let the initial state be 00. The state transition sequence is:

Consider the following circuit with initial state Q0 = Q1 = 0. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.

Consider the following timing diagrams of X and C; the clock period of C <= 40 nanosecond. Which one is the correct plot of Y?

Consider the circuit given below with initial state Q0 =1, Q1 = Q2 = 0. The state of the circuit is given by the value 4Q₂ + 2Q₁ + Q₀

Which one of the following is the correct state sequence of the circuit?

Consider a 4 bit Johnson counter with an initial value of 0000. The counting sequence of this counter is:

A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flipflop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.