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⇱ Intel's Cache Aware Scheduling Presentation At LPC 2025 - Phoronix


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Intel's Cache Aware Scheduling Presentation At LPC 2025

Written by Michael Larabel in Intel on 16 December 2025 at 02:23 PM EST. 5 Comments
One of the exciting Intel innovations to the Linux kernel this year has been around the Cache Aware Scheduling for helping to deliver better performance on modern CPUs with multiple last level caches. The kernel patches have yet to be upstreamed but testing has shown to be quite promising for grouping tasks sharing data to the same LLC domain to help reduce cache misses and cache bouncing. Those wishing to learn more about Cache Aware Scheduling, there was a presentation on it last week by Intel engineers Tim Chen and Chen Yu at the Linux Plumbers Conference 2025 in Tokyo.

We've covered the progressing Cache Aware Scheduling series throughout the year and recently conducted new tests of Cache Aware Scheduling on Intel Xeon 6 as well as CAS also benefiting AMD EPYC performance.

👁 Cache Aware Scheduling benchmarks


For those wishing to learn more about Cache Aware Scheduling straight from the Intel engineers, below is the LPC 2025 video recording and there are also the PDF slides.
Hopefully we see Cache Aware Scheduling make it to the mainline Linux kernel in 2026.

Michael Larabel is the principal author of Phoronix.com and founded the site in 2004 with a focus on enriching the Linux hardware experience. Michael has written more than 20,000 articles covering the state of Linux hardware support, Linux performance, graphics drivers, and other topics. Michael is also the lead developer of the Phoronix Test Suite, Phoromatic, and OpenBenchmarking.org automated benchmarking software. He can be followed via Twitter, LinkedIn, or contacted via MichaelLarabel.com.