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URL: https://www.phoronix.com/news/GCC-More-Zen-6-Tuning-June

⇱ GCC Git Enables Additional Tuning For AMD Zen 6 - Phoronix


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GCC Git Enables Additional Tuning For AMD Zen 6

Written by Michael Larabel in AMD on 4 June 2026 at 08:53 AM EDT. Add A Comment
In addition to Intel adjusting their Nova Lake and Diamond Rapids targets in GCC this week to deal with APX realities, AMD this week also adjusted some tuning bits for their Zen 6 "znver6" target.

These newly-enabled tunings for Zen 6 now fuse ALU with a subsequent conditional jump instruction when the ALU contains a memory operand, fusing ALU with a subsequent conditional jump instruction when the ALU contains both immediate and displacement, and lastly prefering PSHUF to reduce V16QI, V8HI, V8HI, V4SI, V4FI, V2DI modes when LSHR are costlier.

These tunings were already enabled in the GNU Compiler Collection for AMD Zen 4 and Zen 5 processors. So it's a bit surprising these tunings weren't carried over when landing Znver6 in the first place. Also unfortunate that it's coming after the GCC 16.1 stable release where the initial Znver6 support was introduced. Similarly we are still waiting on the Znver6 optimized cost tables / scheduler model to be introduced to the open-source compilers rather than just re-using the prior Zen 4/5 data.

👁 more znver6 tuning


In any event this commit has the latest Znver6 tunings now in GCC 17 Git. Presumably this patch will also get back-ported for the GCC 15.2 point release in the coming months.

Michael Larabel is the principal author of Phoronix.com and founded the site in 2004 with a focus on enriching the Linux hardware experience. Michael has written more than 20,000 articles covering the state of Linux hardware support, Linux performance, graphics drivers, and other topics. Michael is also the lead developer of the Phoronix Test Suite, Phoromatic, and OpenBenchmarking.org automated benchmarking software. He can be followed via Twitter, LinkedIn, or contacted via MichaelLarabel.com.