RADV Vulkan Video Improvements Make It Into Mesa 25.2 For AMD RDNA4 GPUs
Ahead of the Mesa 25.2 code branching / feature freeze expected later this week, last minute feature additions and other changes continue landing in the codebase for these open-source OpenGL and Vulkan drivers. One of the additions today worth mentioning are continued Vulkan Video improvements for AMD Radeon graphics.
Merged today by are some enhancements to RADV's Vulkan Video decode capabilities. This work was carried out by AMD contractor David Rosca, who for months has been working working on their open-source video acceleration code. Besides the RadeonSI/Gallium3D video acceleration code, more recently it has shifted as well to include the RADV driver and Vulkan Video - particularly now that AMD is shifting around their focus of the Radeon Software drivers.
What was merged today is support for Tier 3 decoding with RADV Vulkan Video. As part of that, enabling tiling for video images with VCN5 IP. Video Core Next 5 is the video block with the latest AMD RDNA4 "Navi 4x" GPUs. Tier 3 decoding is only possible with VCN5. The merge request elaborates:
The "VK_VIDEO_DECODE_CAPABILITY_DPB_AND_OUTPUT_COINCIDE_BIT_KHR" allows for using the same video picture resource as the reconstructed picture and decode output picture during the video decode operation in order to conserve device memory.
We'll see what other feature code still manages to land in the coming days for the AMD Radeon drivers and other open-source GPU drivers for Mesa 25.2.
Merged today by are some enhancements to RADV's Vulkan Video decode capabilities. This work was carried out by AMD contractor David Rosca, who for months has been working working on their open-source video acceleration code. Besides the RadeonSI/Gallium3D video acceleration code, more recently it has shifted as well to include the RADV driver and Vulkan Video - particularly now that AMD is shifting around their focus of the Radeon Software drivers.
What was merged today is support for Tier 3 decoding with RADV Vulkan Video. As part of that, enabling tiling for video images with VCN5 IP. Video Core Next 5 is the video block with the latest AMD RDNA4 "Navi 4x" GPUs. Tier 3 decoding is only possible with VCN5. The merge request elaborates:
"Tier3 requires tiling, so this also enables tiling for video images on VCN5.
Adds support for VK_VIDEO_DECODE_CAPABILITY_DPB_AND_OUTPUT_COINCIDE_BIT_KHR, there are no additional DPB images which saves memory."
The "VK_VIDEO_DECODE_CAPABILITY_DPB_AND_OUTPUT_COINCIDE_BIT_KHR" allows for using the same video picture resource as the reconstructed picture and decode output picture during the video decode operation in order to conserve device memory.
We'll see what other feature code still manages to land in the coming days for the AMD Radeon drivers and other open-source GPU drivers for Mesa 25.2.