verilog-design

Here are 3 public repositories matching this topic...

snbk001 / Verilog-Design-Examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F…

verilog testbenches verilog-hdl verilog-programs verilog-project verilog-code verilog-design self-checking

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Verilog

spandanfoldt / Vending-Machine

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This project implements a digital vending machine controller using Verilog HDL, designed as a clean and modular Finite State Machine (FSM). The machine supports five different products, accepts coin input, handles online payment, manages cancel operations, calculates change, and generates a dispense signal when payment conditions are met.

fsm verilog finite-state-machine vivado hdl vending-machine verilog-design

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Verilog

vodopiviz / Dual-Clock-Asynchronous-FIFO-Verilog

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🕒 Implement a Dual-Clock Asynchronous FIFO in Verilog for secure data transfer between independent clock domains in FPGA systems.

fpga async verification verilog synthesis icarus-verilog fifo testbenches fifo-queue digital-design fifo-cache verilog-programs verilog-project verilog-code asic-design verilog-design self-checking cross-clock-domain

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