Primal Origins

Project maintainers

• Jones Alexander, Erick

Quick Start

# Clone
git clone https://codeberg.org/ErickAlexander/Primal-Origins-SoC-IP-Core.git
cd Primal-Origins-SoC-IP-Core

# Verify (1.7M+ tests in Docker)
docker build -t primal-verify . && docker run --rm primal-verify

# Or run directly
pip install hypothesis numpy scipy
python verification/run_all_verification.py

Core RTL: rtl/stack02_hardlaw/smf_unit.sv — The Hard-Law Economic Engine

The Problem

Every financial system has a backdoor.

Software can be patched. Consensus can be bought. Keys can be compromised.

The root cause: economic rules exist as information, which can be copied, modified, and replaced.

The Solution

Encode economic rules as physics.

When you fabricate an integrated circuit, logic gates are physically instantiated in silicon. Changing that logic requires:

1. Redesigning the circuit
2. Manufacturing new photomasks ($1-10M)
3. Fabricating new wafers (3-6 months)
4. Physically replacing every deployed chip

This is not "code is law." This is physics is law.

╔══════════════════════════════════════════════════════════════╗
║ THE HARD-LAW SPLIT (Metal-Mask Constants) ║
╠══════════════════════════════════════════════════════════════╣
║ ║
║ Every transaction through this silicon: ║
║ ║
║ 1.00% → Infrastructure Fund ║
║ 3.00% → Liquidity Pool ║
║ 2.18% → Network Maintenance ║
║ 93.82% → Recipient ║
║ ────────────────────────────── ║
║ 6.18% TOTAL (Immutable in Transistors) ║
║ ║
║ These percentages are not stored in registers. ║
║ They are etched in transistors. ║
║ Changing them requires new silicon. ║
║ ║
╚══════════════════════════════════════════════════════════════╝

Verification

We don't ask you to trust. We ask you to verify.

Test Results

Formal Verification

Civilization Simulation

All evidence is public: evidence/ contains logs, VCD waveforms, and reports.

Architecture

┌─────────────────────────────────────────────────────────────────────┐
│ PRIMAL ORIGINS: OMEGA │
│ 11-Stack SoC Architecture │
├─────────────────────────────────────────────────────────────────────┤
│ │
│ ┌─────────┐ ┌─────────┐ ┌─────────┐ ┌─────────┐ ┌─────────┐ │
│ │ STACK01 │ │ STACK02 │ │ STACK03 │ │ STACK05 │ │ STACK06 │ │
│ │ PUF │ │HARD-LAW │ │BIOLATCH │ │ AES-256 │ │ MESH │ │
│ │Identity │ │ Engine │ │Lifecycle│ │ Crypto │ │ NoC │ │
│ └────┬────┘ └────┬────┘ └────┬────┘ └────┬────┘ └────┬────┘ │
│ │ │ │ │ │ │
│ └────────────┴────────────┴────────────┴────────────┘ │
│ │ │
│ ┌─────────┴─────────┐ │
│ │ STACK07: PULSE │ │
│ │ Governance Core │ │
│ └───────────────────┘ │
│ │
│ ┌──────────────────────────────────────────────────────────────┐ │
│ │ INFRASTRUCTURE │ │
│ │ DFT (JTAG/MBIST/LBIST) • SEU Protection • Clock/Reset │ │
│ └──────────────────────────────────────────────────────────────┘ │
│ │
└─────────────────────────────────────────────────────────────────────┘

Core Innovation: The Hard-Law Engine (Stack 02) — a 3-stage pipelined arithmetic unit computing the 6.18% split using metal-mask constants. See rtl/stack02_hardlaw/smf_unit.sv.

Specifications

Portability: Pure synthesizable SystemVerilog with no process-specific primitives. Integrate into any chip — from 180nm legacy nodes to cutting-edge 3nm, FPGAs (Xilinx/Intel), or custom ASICs.

Applications

Status

Get Involved

Verify the Design

docker build -t primal-verify . && docker run --rm primal-verify

Read the Core

# The Hard-Law Engine
cat rtl/stack02_hardlaw/smf_unit.sv

# Top-level integration 
cat rtl/top/origin_v_core.sv

Contribute

See CONTRIBUTING.md and PARTNERS.md.

Repository Structure

primal-origins-omega/
├── rtl/ # SystemVerilog source (31 modules)
│ ├── stack02_hardlaw/ # The core: Hard-Law Engine
│ ├── stack05_storage/ # AES-256 encryption
│ ├── stack06_mesh/ # 4×4 NoC
│ └── top/ # Top-level integration
├── verification/ # 1.7M+ tests
│ ├── standalone/ # Mathematical verification
│ ├── formal/ # SymbiYosys proofs
│ └── cocotb/ # Python testbenches
├── evidence/ # Execution logs, VCD waveforms
├── docs/ # Technical documentation
├── synthesis/ # Timing constraints, power intent
├── Dockerfile # Reproducible environment
└── README.md # You are here

Documentation

Links

License

CERN Open Hardware Licence v2 – Strongly Reciprocal

You may use, modify, and distribute this design. Modifications must be shared under the same license. See LICENSE.