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Digital Systems: From Logic Gates to Processors

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Digital Systems: From Logic Gates to Processors

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Gain insight into a topic and learn the fundamentals.
4.3

859 reviews

Intermediate level
Some related experience required
Flexible schedule
3 weeks at 10 hours a week
Learn at your own pace

Gain insight into a topic and learn the fundamentals.
4.3

859 reviews

Intermediate level
Some related experience required
Flexible schedule
3 weeks at 10 hours a week
Learn at your own pace

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Assessments

17 assignments

Taught in English
91%
Most learners liked this course

There are 11 modules in this course

This course gives you a complete insight into the modern design of digital systems fundamentals from an eminently practical point of view. Unlike other more "classic" digital circuits courses, our interest focuses more on the system than on the electronics that support it. This approach will allow us to lay the foundation for the design of complex digital systems.

You will learn a set of design methodologies and will use a set of (educational-oriented) computer-aided-design tools (CAD) that will allow you not only to design small and medium size circuits, but also to access to higher level courses covering so exciting topics as application specific integrated circuits (ASICs) design or computer architecture, to give just two examples. Course topics are complemented with the design of a simple processor, introduced as a transversal example of a complex digital system. This example will let you understand and feel comfortable with some fundamental computer architecture terms as the instruction set, microprograms and microinstructions. After completing this course you will be able to: * Design medium complexity digital systems. * Understand the description of digital systems using high-level languages such as VHDL. * Understand how computers operate at their most basic level (machine language).

This module is includes a number of general explanations about how the course will run and about the virtual machine you should install on your computer to answer the different quizzes.<br>This module presents a series of tests you can use to check your level of knowledge about numbering systems and the use of pseudocode to describe algorithms.

What's included

3 videos14 readings2 assignments

3 videosTotal 39 minutes
  • Course presentation2 minutes
  • L0.1. Binary numeration system19 minutes
  • L0.2. Algorithm representation in pseudocode17 minutes
14 readingsTotal 140 minutes
  • Course Organization10 minutes
  • Syllabus and bibliography10 minutes
  • CHANGES IN COURSERA10 minutes
  • Grading policy10 minutes
  • Certification10 minutes
  • Solving doubts and technical issues10 minutes
  • Free for the UAB community10 minutes
  • FAQs10 minutes
  • About the forums10 minutes
  • README10 minutes
  • How to install the virtual machine (VM)10 minutes
  • FAQs about installing the VM10 minutes
  • Table of contents10 minutes
  • PDF file10 minutes
2 assignmentsTotal 44 minutes
  • Practice quiz 0.1: Numeration systems30 minutes
  • Practice quiz 0.2: Pseudocode14 minutes

<b><font size=4 color=#B22222><b>Click on "v More" to read the purpose of this module</b></font> </b> <br/><br/>This module is an introduction to Digital Systems. Here you will find:<ol><li>A set of videos_L covering issue 1 and the corresponding exercises, </li><li>Two videos_P introducing the processor that we will design along the course, and</li><li>Some video-based explanations; a wiki and some FAQs about how VerilUOC_Desktop tool functions.<br/> You will have to use VerilUOC_Desktop in the next module</li></ol> Read the "Lesson Index" in the "Index and PDF files" section and the "README" in the VerilUOC_Desktop section for more information.

What's included

5 videos3 readings2 assignments

5 videosTotal 71 minutes
  • L1.1. Digital systems12 minutes
  • L1.2 Digital system description 11 minutes
  • L1.3 Digital electronic systems17 minutes
  • P1.1. Processor: Specification 12 minutes
  • P1.2. Examples of Programs 20 minutes
3 readingsTotal 30 minutes
  • Lesson index10 minutes
  • PDF files10 minutes
  • Solved exercises10 minutes
2 assignmentsTotal 60 minutes
  • Graded quiz 130 minutes
  • Practice quiz 130 minutes

<b><font size=4 color=#B22222><b>Click on "v More" to read the purpose of this module</b></font> </b> <br/><br/>This module introduces combinational circuits, logic gates and boolean algebra, all of them items necessary to design simple combinational circuits.<br/> Read the "Index of lessons" for more information. <br/><br/><b>To solve the exercises in this module you will need to use VerilUOC_Desktop. Look at the module "VerilUOC_Desktop tools" to learn how to use it.</b>

What's included

5 videos3 readings2 assignments

5 videosTotal 101 minutes
  • L2.1. Combinational circuits23 minutes
  • L2.2. Boolean Algebra26 minutes
  • L2.3. NAND, NOR, XOR, NXOR, TRI-STATE27 minutes
  • P2.1. Functional specification 13 minutes
  • P2.2. Structural specification 11 minutes
3 readingsTotal 30 minutes
  • Lesson index10 minutes
  • PDF files10 minutes
  • Solved exercises10 minutes
2 assignmentsTotal 60 minutes
  • Graded quiz 230 minutes
  • Practice quiz 230 minutes

<b><font size=4 color=#B22222><b>Click on "v More" to read the purpose of this module</b></font> </b><br/><br/>From this module you will need to use VerilUOC_Desktop to do some of the exercises in the quizzes. VerilUOC_Desktop is a software package based on Logisim, enhanced with a number of modules to enable:<ul><li>Enter Boolean equations (BoolMin),</li><li>Enter digital circuits and check them according the problem statement (VerilCirc), and</li><li>Enter chronograms (time-charts) and check that they are correct (VerilChart).</li></ul>This section contains two videos explaining how these three tools work. By now you only need to use VerilCirc and BoolMin, so if you are pushed for time, you might postpone VerilChart for later. Obviously, it is impossible to cover in these two videos all eventualities you can find while working with VerilUOC_Desktop tools. In case of doubt, look at the VerilUOC_Desktop wiki, look at the FAQs or post your problems in the forums. There are specific forums for VerilCirc, BoolMin and VerilChart.

What's included

2 videos3 readings

2 videosTotal 33 minutes
  • Introduction to VerilUOC_Desktop (I). Logisim and VerilCirc21 minutes
  • Introduction to VerilUOC_Desktop (II). BoolMin and VerilChart12 minutes
3 readingsTotal 30 minutes
  • Table of contents10 minutes
  • VerilUOC_desktop wiki10 minutes
  • VerilUOC_desktop FAQs10 minutes

<b><font size=4 color=#B22222><b>Click on "v More" to read the purpose of this module</b></font> </b><br/><br/>We continue the study of combinational circuits. While in the previous module we were working on the classical design techniques of combinational circuits, this one is focused on other issues such as a brief introduction to computer aided design tools (CAD tools), or the direct synthesis of combinational circuits from its algorithmic description.<br/> Read the "Lesson index" for more information. <br><br/><b>To solve the exercises in this module VerilUOC_Desktop is needed. </b>Remember that the module "VerilUOC_Desktop tols" contains all the information you need about this tool.

What's included

5 videos3 readings2 assignments

5 videosTotal 84 minutes
  • L3.1. Combinational circuit synthesis tools22 minutes
  • L3.2. Propagation time15 minutes
  • L3.3. Other logic blocks24 minutes
  • L3.4. Programming language structures 14 minutes
  • P3.1. Structural specification (continuation) 9 minutes
3 readingsTotal 30 minutes
  • Lesson index10 minutes
  • PDF files10 minutes
  • Solved exercises10 minutes
2 assignmentsTotal 46 minutes
  • Graded quiz 316 minutes
  • Practice quiz 330 minutes

<b><font size=4 color=#B22222><b>Click on "v More" to read the purpose of this module</b></font> </b><br/><br/>Arithmetic circuits are an essential part of many digital circuits and thus deserve a particular treatment. <ul><li> The first part of this module presents some implementations of the basic arithmetic operations. Only operations with naturals (non-negative integers) are considered. </li><li>The second part of this module introduces the basics of VHDL with the goal of providing enough knowledge to understand its usage throughout this course and start developing basic hardware models.</li></ul>

What's included

10 videos9 readings1 assignment

10 videosTotal 167 minutes
  • L4.1 Arithmetic blocks27 minutes
  • Lecture 4.2 (1outof2): Introduction to VHDL - Lexicon, syntax and structure9 minutes
  • Lecture 4.2 (2outof2): Introduction to VHDL - Lexicon, syntax and structure12 minutes
  • Lecture 4.3 (1outof2): Introduction to VHDL - Sequential sentences11 minutes
  • Lecture 4.3 (2outof2): Introduction to VHDL - Sequential sentences13 minutes
  • Lecture 4.4 (1outof2): Introduction to VHDL - Concurrent sentences12 minutes
  • Lecture 4.4 (2outof2): Introduction to VHDL - Concurrent sentences9 minutes
  • L4.2 Short introduction to VHDL I (OLD VERSION)22 minutes
  • L4.3 Short introduction to VHDL II (OLD VERSION)19 minutes
  • L4.4 Short introduction VHDL III (OLD VERSION)33 minutes
9 readingsTotal 90 minutes
  • IMPORTANT - README10 minutes
  • Lesson index10 minutes
  • PDF files10 minutes
  • Lesson index (OLD VERSION)10 minutes
  • PDF files (OLD VERSION)10 minutes
  • IMPORTANT - README10 minutes
  • No lecture about the processor in this module . Next video will be P5.1.10 minutes
  • About the exercises (README)10 minutes
  • Solved exercises - Arithmetic circuits10 minutes
1 assignmentTotal 30 minutes
  • Practice quiz 430 minutes

<b><font size=4 color=#B22222><b>Click on "v More" to read the purpose of this module</b></font> </b><br/><br/>This is the first module dedicated to Sequential Circuits (Digital Systems with Memory).<br/><b>To solve the quizzes you will need VerilUOC_Desktop</b>.

What's included

7 videos3 readings2 assignments

7 videosTotal 79 minutes
  • L5.1 Sequential circuits11 minutes
  • L5.2 Explicit functional description16 minutes
  • L5.3 Latches and flip-flops16 minutes
  • L5.4 Synthesis from tables9 minutes
  • L5.5 An example of synthesis2 minutes
  • P5.1 Combinational blocks13 minutes
  • P5.2 Sequential blocks12 minutes
3 readingsTotal 30 minutes
  • Lesson index10 minutes
  • PDF files10 minutes
  • Solved exercises10 minutes
2 assignmentsTotal 40 minutes
  • Graded quiz 530 minutes
  • Practice quiz 510 minutes

<b><font size=4 color=#B22222><b>Click on "v More" to read the purpose of this module</b></font> </b><br/><br/>This second module dedicated to Sequential Circuits deals with particular sequential circuits that are building blocks of larger circuits, namely registers, counters and memory blocks.

What's included

4 videos3 readings2 assignments

4 videosTotal 59 minutes
  • L6.1. Registers18 minutes
  • L6.2. Counters16 minutes
  • L6.3. Memories15 minutes
  • P6.1. Sequential blocks (continuation)11 minutes
3 readingsTotal 30 minutes
  • Lesson index10 minutes
  • PDF files10 minutes
  • Solved exercises10 minutes
2 assignmentsTotal 60 minutes
  • Graded quiz 630 minutes
  • Practice quiz 630 minutes

<b><font size=4 color=#B22222><b>Click on "v More" to read the purpose of this module</b></font> </b><br/><br/>This module deals with two topics: <ol><li>In previous lessons, the relation between algorithms (programming language structures) and combinational circuits has been commented. This relation also exists between algorithms and sequential circuits. We will explore this relation in the current module.</li><li>The second topic we will see is the definition and VHDL modelling of Finite State Machines.</li></ol>

What's included

5 videos4 readings2 assignments

5 videosTotal 81 minutes
  • L7.1. Sequential implementation of algorithms15 minutes
  • L7.2. Finite state machines16 minutes
  • L7.3. Examples of finite state machines23 minutes
  • P7.1. Sequential blocks (continuation)11 minutes
  • P7.2. Instructions, control, complete circuit17 minutes
4 readingsTotal 40 minutes
  • Lesson index10 minutes
  • PDF files10 minutes
  • Solved exercices10 minutes
  • QUIZ 7 INSTRUCTIONS10 minutes
2 assignmentsTotal 60 minutes
  • Graded quiz 730 minutes
  • Practice quiz 730 minutes

<b><font size=4 color=#B22222><b>Click on "v More" to read the purpose of this module</b></font> </b><br/><br/>This last module presents some basic information about manufacturing technologies, as well as about implementation strategies, and synthesis and implementation tools.

What's included

4 videos2 readings2 assignments

4 videosTotal 47 minutes
  • L8.1. Physical implementation 10 minutes
  • L8.2. Implementation strategies and synthesis tools 11 minutes
  • P8.1. Test 12 minutes
  • P8.2. Design methods15 minutes
2 readingsTotal 20 minutes
  • Lesson index10 minutes
  • PDF files10 minutes
2 assignmentsTotal 38 minutes
  • Graded quiz 830 minutes
  • Practice quiz 88 minutes

´´

What's included

3 readings

3 readingsTotal 30 minutes
  • Farewell10 minutes
  • What have we learned?10 minutes
  • How can I go deeper into the topic?10 minutes

Instructors

Instructor ratings
4.4 (141 ratings)
Universitat Autònoma de Barcelona
2 Courses149,932 learners
Universitat Autònoma de Barcelona
2 Courses149,932 learners
Universitat Autònoma de Barcelona
2 Courses149,932 learners

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Showing 3 of 859

SM
·

Reviewed on Jul 10, 2018

The course goes from a logic gate level to that of a processor in a smooth manner covering many concepts enroute

SA
·

Reviewed on Jul 10, 2022

The most interesting part of this course, for me, was the graded quiz. It was challenging , but nice.I really learnt a lot.Thank you

SN
·

Reviewed on Mar 20, 2020

Pretty awesome, the course gives you a good understanding of all basic concepts and the practice, extra and graded problems make you intimately familiar with its applications.

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