Game-Changer for Local LLMs: AMD Medusa Halo Leak Points to 384-Bit LPDDR6 Bandwidth

Moore’s Law Is Dead has leaked new details on AMD’s upcoming Medusa Halo APU, the direct successor to Strix Halo. For enthusiasts focused on running large language models locally, this is an important development, as Medusa Halo addresses the biggest bottleneck of its predecessor: memory bandwidth.

From Strix Halo to Medusa Halo

Strix Halo (Ryzen AI Max+ 395) was the first real step toward compact systems capable of loading very large models, with support for up to 128 GB of unified memory. While this allowed 70B parameter LLMs to fit in memory, inference speed was limited by the 256-bit LPDDR5X memory bus, which capped bandwidth at about 256 GB/s.

Medusa Halo takes that foundation and expands it. The new platform introduces support for LPDDR6 through a 384-bit memory bus, using the new FP12 socket. This represents a 50% wider interface combined with a faster memory standard. The exact RAM capacities are not yet known, but the shift alone points to a dramatic increase in throughput.

Memory Bandwidth: The Key Upgrade

For local LLM inference, bandwidth directly impacts tokens per second. Medusa Halo’s 384-bit LPDDR6 controller scales theoretical bandwidth into the range of modern discrete GPUs:

• At 10,000 MT/s → 480 GB/s
• At 12,800 MT/s → 614.4 GB/s
• At 14,400 MT/s → 691.2 GB/s

This is nearly double or triple what Strix Halo offered and positions Medusa Halo’s unified memory bandwidth in the same class as high-end workstation GPUs, though still short of upcoming GDDR7 cards like the RTX 5090 at 1.79 TB/s.

RDNA 5 GPU Integration

Medusa Halo also upgrades the integrated GPU. According to the leak, it features 48 RDNA 5 compute units (CUs), up from Strix Halo’s 40 RDNA 3.5 CUs. Beyond the raw increase in CU count, RDNA 5 is expected to be far more efficient, as AMD is reusing desktop GPU chiplets (codenamed AT3) within the APU package. This could improve parallelism for AI workloads and help with prompt processing tasks.

What We Don’t Know Yet

The leak confirms the bus width and GPU details but does not provide final memory capacities. Without that, it is too early to estimate the maximum model size Medusa Halo can handle, or how tokens-per-second performance will compare against dedicated GPUs.

Early Outlook

For local LLM inference, Strix Halo made large model loading possible. Medusa Halo looks set to make it fast and responsive. The move from 256-bit LPDDR5X to 384-bit LPDDR6 is the defining upgrade, with bandwidth gains in the 480–691 GB/s range depending on memory speeds. Coupled with a stronger RDNA 5 GPU block, Medusa Halo is shaping up to be a much more capable APU for local AI systems.

We will need to wait for further leaks or official announcements to know how much memory AMD intends to ship with these APUs, which will ultimately decide whether Medusa Halo can comfortably handle the next generation of quantized LLMs.

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