RISC-V With Linux 6.18 Brings Support For MIPS Vendor Extensions

Written by Michael Larabel in RISC-V on 29 September 2025 at 08:45 AM EDT. Add A Comment

Back during the Linux 6.17 merge window the RISC-V changes were rejected as "garbage" for being submitted too late in the merge window and with some code choices that upset Linus Torvalds. With lessons learned, the RISC-V changes for Linux 6.18 were submitted today during the first official day of this new kernel cycle.

The first batch of RISC-V feature updates were submitted for Linux 6.18. Standing out is support for detecting and utilizing MIPS vendor extensions for RISC-V. Not to be confused with the defunct MIPS64 CPU ISA but rather MIPS' additions for the RISC-V world now that MIPS Tech is focused on RISC-V processors.

👁 MIPS P8700 diagram

Initially this MIPS extension work for RISC-V is focused around MIPS P8700 specific work and making use of their new "PAUSE" implementation.

"- Replacement of __ASSEMBLY__ with __ASSEMBLER__ in header files (other architectures have already merged this type of cleanup)

- The introduction of ioremap_wc() for RISC-V

- Cleanup of the RISC-V kprobes code to use mostly-extant macros rather than open code

- A RISC-V kprobes unit test

- An architecture-specific endianness swap macro set implementation, leveraging some dedicated RISC-V instructions for this purpose if they are available

- The ability to identity and communicate to userspace the presence of a MIPS P8700-specific ISA extension, and to leverage its MIPS-specific PAUSE implementation in cpu_relax()

- Several other miscellaneous cleanups"

More details on these RISC-V changes for Linux 6.18 via this pull request.