RISC-V News Archives

An important one-liner is set to come for Linux 7.2 to enable ESWIN SoC support by default for RISC-V kernel builds. This change will allow default RISC-V kernel builds in turn to boot on the likes of SiFive's HiFive Premier P550 developer board.

In addition to the SpacemiT K1 and K3 RISC-V SoC Device Tree updates sent out last week, the RISC-V T-HEAD Device Tree "DT" changes were also sent out last week ahead of the upcoming Linux 7.2 kernel merge window.

In addition to Apple M3 Device Trees for Linux 7.2, the SpacemiT RISC-V SoCs are seeing some notable Device Tree improvements with this next version of the Linux kernel.

The BeagleV Ahead is an open-source RISC-V single board computer S(BC) built around the quad-core TH1520 SoC. With the Linux 7.1 mainline kernel there is HDMI display support coming now that the Device Tree bits have been added.

The SpacemiT K3 is exciting as one of the first RISC-V RVA23 designs coming to market. For the Linux 7.0 kernel there is initial K3 support in the mainline kernel while the upcoming Linux 7.1 merge window is expected to land more K3 enablement.

RISC-V processor IP purveyor SiFive just announced they have raised $400 million USD in an over-subscribed Series G financing round. This latest funding is so they can further focus on delivering high performance RISC-V designs for the data center.

In addition to RISC-V discontinuing its eXecute In Place "XIP" kernel support for Linux 7.1, there is an optimized strnlen() function coming for Linux 7.1 on RISC-V as well as some other optimized functions.

Introduced in Linux 5.13 back in 2021 was eXecute In Place "XIP" support for RISC-V that allows for the kernel image to be executed from ROM. The intent is on allowing the kernel to run from non-volatile storage like NOR flash that is directly addressable by the CPU and to reduce RAM usage. But after RISC-V XIP support is broken for months at a time, the feature is now set to be retired from the mainline kernel.

The current crop of RISC-V SoCs are still much slower than alternative CPU architectures and lead to much longer build times for Fedora packages as a result. There's hope with next-gen RISC-V processors being faster but for now even compiling Binutils as an example is around five times slower than x86_64 -- and that's with disabling compiler link-time optimizations (LTO) for RISC-V to avoid an even longer build process.

The RISC-V architecture updates have been merged for Linux 7.0 with a few items to note.

While many open-source enthusiasts like to flaunt RISC-V as not having the security challenges as x86_64 CPUs have seen over the past several years with various speculative execution / side-channel attacks and arguing for the benefits of an open-source ISA in stronger security, in practice it's not so clear-cut. Security researchers at Germany's CISPA Helmholtz Center for Information Security have found current RISC-V CPU implementations coming up short for their actual security.

Similar to what has been available on Intel and AMD processors for users with the shadow stack for control-flow integrity, Linux on RISC-V is finally ready to roll-out its user-space control-flow integrity support.

Increasingly complex RISC-V cores aren't magically immune to the speculative execution / side-channel vulnerabilities that have rattled the x86_64 and ARM64 landscape for years. Following recent work on Spectre V1 handling for RISC-V in the Linux kernel, merged this weekend for Linux 6.19-rc5 is another RISC-V attack vector safeguard.

The latest work by Qualcomm on the RISC-V CPU architecture is sending out their first non-RFC patch series for enabling Reliability, Availability and Serviceability (RAS) support by making use of the RISC-V RERI specification. This RISC-V RAS support is useful for conveying hardware errors to users and will be especially important with future RISC-V Linux servers.

Spectre V1 mitigations in the Linux kernel are coming for RISC-V with newer RISC-V core designs being vulnerable to Spectre Variant One style attacks.

With the first of RISC-V RVA23-compatible hardware expected to be released in 2026, we are beginning to see more Linux developers prepare for this RVA23 profile and the now-mandated extensions. Sent out this week was an initial "request for comments" patch series on RVA23 adjustments for the Linux kernel.

An acquisition announcement that flew under the radar yesterday but then I only noticed today with a GCC MAINTAINERS file update, "with the acquisition of Ventana Microsystems by Qualcomm..." Qualcomm has acquired Ventana as a RISC-V high performance CPU start-up.

The RISC-V CPU architecture changes have been merged for the in-development Linux 6.19 kernel.

An interesting anecdote from this week's batch of RISC-V fixes for the Linux 6.18 kernel exposed that the MIPS RISC-V/JEDEC vendor ID was wrong for code merged at the start of the kernel cycle. The testing hadn't caught it either as the QEMU emulation also ended up inadvertently using the wrong vendor ID too.

Following the mainline Linux kernel support for the VisionFive 2 RISC-V single board computer from StarFive, Linux kernel patches are on the way for their new VisionFive 2 Lite low-cost offering. With the StarFive VisionFive 2 Lite this RISC-V board can be procured for as little as $19.9 USD as one of the cheapest yet fairly capable RISC-V SBCs.

For those looking for a new RISC-V desktop option, ESWIN is launching a EBC7702 mini-DTX board powered by the EIC7702X dual-die SoC. The EBC7702 Mini-DTX is aiming for developers who want RISC-V under their desk for working on AI and other development tasks.

Following last week's RISC-V pull request that brought support for the MIPS Vendor Extensions and other changes plus separately the SoC pull that added mainline ESWIN EIC7700 SoC support and the HiFive Premier P550, a secondary round of RISC-V architecture updates was submitted for the Linux 6.18 merge window.

Linus Torvalds has come out strong against proposed support for RISC-V big endian capabilities within the Linux kernel.

Back during the Linux 6.17 merge window the RISC-V changes were rejected as "garbage" for being submitted too late in the merge window and with some code choices that upset Linus Torvalds. With lessons learned, the RISC-V changes for Linux 6.18 were submitted today during the first official day of this new kernel cycle.

Patches were posted this past weekend for enabling the mainline Linux kernel to run on the Tenstorrent Blackhole SoC of A0 silicon on the Blackhole P100 and P150 PCIe accelerator cards.

Imagination's open-source PowerVR kernel graphics driver for a while has seen patches extending it to work on RISC-V given that some RISC-V hardware coming to market has featured PowerVR graphics IP. With the upcoming Linux 6.18 kernel that work is landing along with enabling support for the T-HEAD TH1520's GPU.

Linux kernel patches for supporting RISC-V's Zalasr ISA extension are now under review. This extension provides "real" load acquire/store release instructions for RISC-V processors.

The RISC-V architecture feature updates were merged on Friday for the Linux 6.16 merge window that is set to end on Sunday with the Linux 6.16-rc1 release.

With Red Hat Enterprise Linux 10 providing a RISC-V developer preview, CentOS is now in turn also providing initial RISC-V CPU ISA support.

Queued within the development tree for the RISC-V processor code for the Linux kernel is supporting several new vendor-specific ISA extensions for SiFive RISC-V CPU cores.

As another alternative to the likes of the SiFive HiFive Premier P550 RISC-V developer board, the Andes Voyager is in the process of seeing patches reviewed for mainline Linux kernel support.

Merged last year in Linux 6.11 was getrandom() support in the vDSO for x86/x86_64 and then in Linux 6.12 was extended to LoongArch and ARM64. With the upcoming Linux 6.16 cycle, this support for faster while still secure RNG for user-space is set to come to RISC-V.

Merged on Friday for the nearly-over Linux 6.15 merge window were the RISC-V CPU architecture updates for this next kernel release.

Cloud Hypervisor began as an open-source Intel software project more than a half-decade ago with an emphasis on security and cloud deployments while leveraging the Rust programming language. With time its scope has broadened a lot as has its industry adoption. With time it added ARM64 support and recruited AMD, Ampere Computing, Microsoft, and others as its supporters while being folded into the Linux Foundation. The latest expansion for the project is introducing experimental RISC-V 64-bit support.

Patches were posted to the Linux Kernel Mailing List this morning for wiring up the ESWIN EIC7700 RISC-V SoC support and the most notable board using this SoC so far, the SiFive HiFive Premier P550.

The RISC-V CPU architecture feature updates have now been submitted and merged for the nearly-over Linux 6.14 merge window.

The upcoming Linux 6.14 kernel is poised to introduce initial support for SpacemiT platforms, the Chinese computing chip company developing "next-generation RISC-V high-performance CPUs." For this next Linux kernel release the SpaceMiT Key Stone K1 octa-core RISC-V AI CPU with SpacemiT X60 cores will see support.

Linux has supported KVM virtualization with RISC-V for several years while now patches are pending to introduce Xen hypervisor support for this CPU architecture for RISC-V guests.

Upstreamed to LLVM/Clang overnight is now targeting support for the SiFive P550 RISC-V core with the "-mcpu=sifive-p550" option.

RISC-V on the software front made very nice progress over the past year with a lot of Linux kernel and toolchain improvements, new targets being enabled, and new instructions being supported along with other additions for improving the overall RISC-V software ecosystem. When it comes to hardware though most of the readily available RISC-V systems are painstakingly slow and the more performant/featureful options are much harder to come by.

Going back to April 2024, SiFive announced the HiFive Premier P550 as an interesting RISC-V developer board to succeed their HiFive Unleashed that was a nice little RISC-V board. There were delays in shipping the HiFive Premier P550 but they have been making progress and are now ready to ship Ubuntu 24.04 LTS pre-installed on this RISC-V board. They have also lowered the pricing on these RISC-V boards.

The Linux 6.8 kernel merged the Imagination PowerVR driver as a new open-source driver for supporting the PowerVR "Rogue" graphics architecture and being developed in tandem by Imagination Tech with their upstream Mesa Vulkan driver. Initially this PowerVR driver was catering to ARM SoCs with the Rogue graphics while now the open-source driver is being extended to work on RISC-V too.

Patches from a Bytedance engineer for the Linux kernel allow for overcoming the current 4K page size limitation of RISC-V and introduce a new 64K page size option.

The RISC-V CPU port updates have been sent out for the in-development Linux 6.13 kernel.

MIPS has begun working on the open-source compiler toolchain support for their P8700 RISC-V based processors. Initial patches posted today bring-up the MIPS P8700 RISC-V support for the LLVM compiler stack.

It looks like the upcoming Linux 6.13 cycle will be adding RISC-V support for user-space pointer masking and tagged address ABI.

Earlier this year SiFive announced the HiFive Premier P550 RISC-V development board with plans for shipping in July. That timeframe for shipping since passed but SiFive today issued a new update on their RISC-V development board.

The RISC-V architecture updates have been submitted for the Linux 6.12 kernel cycle. More RISC-V CPU ISA extensions are being supported along with enabling some additional kernel features for this CPU architecture.

Back in June it was teased that Framework Computer in collaboration with DeepComputing would be releasing a RISC-V motherboard for the Framework Laptop 13. That RISC-V laptop motherboard has yet to be officially released but Linux kernel patches were posted today for enabling the DeviceTree support so Linux can boot on this upcoming board.

While RISC-V processors don't need to worry about Meltdown and Spectre or have any other severe CPU vulnerabilities at the moment, with the upcoming Linux 6.12 kernel the RISC-V code is set to enable the generic CPU vulnerabilities support.