sky130

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

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• Verilog

The next generation of OpenLane, rewritten from scratch with a modular architecture

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• Python

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

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• Verilog

Index of the fully open source process design kits (PDKs) maintained by Google.

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Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns

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• SourcePawn

Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

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JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.

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• Verilog

Raw data collected about the SKY130 process technology.

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• Jupyter Notebook

Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license

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• Verilog

Flip flop setup, hold & metastability explorer tool

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• Jupyter Notebook

A simple MOSFET model with only 5-DC-parameters for circuit simulation

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This repo contains the code that runs RL+GNN to optimize LDOs in SKY130 process.

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• Jupyter Notebook

This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK

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KLayout technology files for Skywater SKY130

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• Makefile

Fully-differential asynchronous non-binary 12-bit SAR-ADC

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• Verilog

Primitives for SKY130 provided by SkyWater.

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open source hardware synthesis. SystemVerilog, VHDL and ABEL-HDL to gate-level netlists

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• C

Reinforcement learning assisted analog layout design flow.

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• Python

SRAM build space for SKY130 provided by SkyWater.

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"High density" digital standard cells for SKY130 provided by SkyWater.

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• Verilog