Digital logic design tool and simulator
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- Java
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Haskell to VHDL/Verilog/SystemVerilog compiler
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- Haskell
Hardware Description Languages
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VUnit is a unit testing framework for VHDL/SystemVerilog
unit-testing asic fpga vhdl verification testbench verilog-hdl systemverilog-hdl universal-verification-methodology
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- VHDL
An abstraction library for interfacing EDA tools
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- Python
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
python c fpga hls hardware vhdl pipelines open-source-hardware high-level-synthesis hardware-description-language fpga-accelerators fpga-acceleration fpga-programming hardware-description
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- VHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
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- VHDL
The PoC Library has been forked to github.com/VHDL/PoC. See new address below
python asic fpga simulation vhdl verification xilinx synthesis regression-testing altera hardware-designs lattice hardware-libraries poc-library vlsi testbenches hardware-modules osvvm uvvm vunit
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- VHDL
A List of Free and Open Source Hardware Verification Tools and Frameworks
python coverage awesome hardware vhdl verification verilog awesome-list formal-verification constrained-random-verification
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