systemverilog-hdl

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

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• Assembly

VUnit is a unit testing framework for VHDL/SystemVerilog

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• VHDL

A Framework for Design and Verification of Image Processing Applications using UVM

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• SystemVerilog

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

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• Python

A SystemVerilog source file pickler.

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• Rust

Simple single-port AXI memory interface

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• SystemVerilog

A simple UVM example with DPI

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• SystemVerilog

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore

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• SystemVerilog

Contains commonly used UVM components (agents, environments and tests).

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• SystemVerilog

A Tcl-Library for scripted HDL generation

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• Tcl

An FPGA design for simulating biological neurons

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• SystemVerilog

UVM

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• SystemVerilog

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• SystemVerilog

ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor

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• SystemVerilog

Getting started with SystemVerilog: Hardware Description Language for design and verification.

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• SystemVerilog

A simple UVM testbench using UVM Connect and Octave

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• SystemVerilog

Bit-Efficient Replicator Tech for X, Y, Z axis motor control (3D printers)

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• VHDL

RISC-V processor co-simulation using SystemVerilog HDL and UVM.

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• SystemVerilog

Final Project third-perspective-shooting video game PokeHead and some other lab codes and design of ECE385 Digital Systems Laboratory

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• C

AXI to Peripheral Interconnect

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• SystemVerilog