softcore

A FPGA friendly 32 bit RISC-V CPU implementation

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• Assembly

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

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• SystemVerilog

80186 compatible SystemVerilog CPU core and FPGA reference design

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• C++

A Forth CPU and System on a Chip, based on the J1, written in VHDL

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• VHDL

SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype

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• Scala

RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card

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• SystemVerilog

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

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• Scala

Mostly AVR compatible FPGA soft-core

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• Verilog

RISC-V implementation of RV32I for FPGA board Tang Nano 20K utilizing on-board burst SDRAM, flash and SD card

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• SystemVerilog

u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV

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• Verilog

Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware

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• Verilog

Soft-core uController POC using the risc16f84 pic clone and sdcc c-compiler

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• C

A 16 bit softcore processor implemented in VHDL

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• VHDL

Trabalho de conclusão de curso de título Integração de ramais analógicos com FPGA utilizando processador softcore

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• C

A cycle-accurate VHDL model for MCS-48 and UPI devices

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• VHDL

A RISC/CISC 32 bit softcore processor in VHDL

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• VHDL

Trying to implement a soft core SoC

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• Verilog

PIC16F84 soft-core RTL

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• VHDL

Quick demo for Lattice FPGA with RiscV

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• HTML

Set of basic image processing systems implemented for learning purposes.

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• VHDL