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URL: https://github.com/topics/soc-fpga

⇱ soc-fpga · GitHub Topics · GitHub

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soc-fpga

Here are 12 public repositories matching this topic...

WangXuan95 / Zynq-Tutorial

使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例

zynq vivado zedboard petalinux block-design soc-fpga zynq-7020

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👁 HPS2FPGAmapping

robseb / HPS2FPGAmapping

SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)

linux fpga python-script intel bootloader altera can-bus fpga-soc embedded-linux quartus-prime intel-fpga altera-fpga hps fpga-configuration soc-fpga fpga-fabric mapping-hps-peripherals rsyocto

Updated
Verilog

nekosilverfox / ZYNQ

⚙️ 基于 Zynq-7 全可编程 SoC 的设计

sdk fpga zynq verilog xilinx vivado zynq-7010 zynq-7000 soc-fpga zynq-7020 soc-design

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HTML

👁 meta-intelfpga

robseb / meta-intelfpga

Yocto Project BSP meta-layer for Intel (ALTERA) SoC-FPGAs (SoCFPGA) - with step by step guide

linux-distribution yocto-layer altera yocto-meta development-tools cyclone-v intel-fpga arria-v arria10 intel-soc-fpgas fpga-configuration soc-fpga soc-fpga-linux fpga-fabric bsp-layer rsyocto

Updated
BitBake

👁 Django2FPGAdemo

robseb / Django2FPGAdemo

Demonstration how to build a Management Web interface to interact with the FPGA fabric and change the FPGA configuration with the Django Framework

django django-framework adc altera sensor-data cyclone-v de10nano intel-fpga de10-nano de10-standard fpga-configuration soc-fpga fpga-data fpga-fabric rsyocto

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Python

robseb / LinuxVSCppFPGA

C++ examples for accessing FPGA Soft-IP and Hard-IP with embedded Linux for Intel (ALTERA) SoC-FPGAs (Cyclone V)

microsoft-visual-studio embedded-linux cyclone-v soc-fpga soc-fpga-linux rsyocto linux-development

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C

👁 NIOSII_EclipseCompProject

robseb / NIOSII_EclipseCompProject

Automatically create a NIOS II Eclipse Project with the latest FreeRTOS Version, the Intel hwlib and more...

c eclipse python-script intel freertos cyclone-v quartus intel-fpga max10 nios-ii arria-v arria10 intel-quartus-prime soc-fpga custom-eclipse

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C

design-gateway / nvmeg4ip-dma-plnx-demo

NVMe Gen4 Host IP DMA with PetaLinux Demo on ZCU106

fpga zynq ssd nvme petalinux xilinx-fpga dma axi-dma xilinx-zynq soc-fpga

Updated

raetro / raetro_system_u-boot

Rætro U-Boot Bootloader

fpga bootloader u-boot soc-fpga

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C

design-gateway / random-nvme-blkdev-petalinux

Random-access NVMe block-device demo on ZCU106 using rmNVMe-IP for PetaLinux, featuring performance tests and NVMe management examples.

fpga zynq ssd nvme petalinux xilinx-fpga dma xilinx-zynq soc-fpga

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yoitsmeg / nvmeg4ip-dma-plnx-demo

🚀 Accelerate NVMe Gen4 SSD data transfers using the NVMeG4-IP core and DMA on PetaLinux, achieving high speeds while reducing CPU load.

fpga zynq ssd nvme petalinux xilinx-fpga dma axi-dma xilinx-zynq soc-fpga

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rokzitko / PulsePins

PulsePins provides a programmable timing core for dozens of digital pins, suitable for pulse sequences, triggers, multiplexing, and general lab ‘digital glue’

fpga timing instrumentation verilog systemverilog lab-automation experimental-physics quantum-control triggering soc-fpga pulse-sequencer

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C++

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