soc-design

Here are 27 public repositories matching this topic...

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

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Python

arm-education / Introduction-to-SoC-Design-Education-Kit

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Education kit for teaching introductory Arm-based system-on-chip design on FPGA with lectures and practical labs (educational)

arm fpga cortex-m vhdl cmsis hardware-designs soc teaching-materials arm-cortex-m0 system-on-chip amba ahb soc-design keil-mdk system-on-chip-design design-start education-kit

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HTML

arm-education / Advanced-System-on-Chip-Design-Education-Kit

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Education kit for teaching advanced Arm Cortex-A system-on-chip design on FPGA platforms with lectures and hands-on labs (educational)

arm fpga vhdl embedded-systems armv7 vivado hardware-designs teaching-materials cortex-a zybo amba cortex-a9 arm-cortex-a9 soc-design system-on-chip-design zybo-z7-10 education-kit

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HTML

arm-education / Modern-System-on-Chip-Design-on-Arm

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Textbook for advanced students and engineers on modern SoC design using Arm Cortex-A: architecture, interconnects, validation, and fabrication (educational)

arm textbook hardware-designs computer-architecture systemc soc vlsi formal-verification fpga-soc cortex-a system-design soc-design electronic-system-level system-on-chip-design arm-cortex-a

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arm-education / System-on-Chip-Design-with-Arm-Cortex-M-Processors

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Reference book for SoC and FPGA designers integrating Arm Cortex-M processors with AMBA bus architectures (educational)

arm fpga cortex-m embedded-systems software-design amba arm-cortex-m hardware-design soc-design keil-mdk system-on-chip-design bus-architecture cortex-m-processors reference-book

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nekosilverfox / ZYNQ

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⚙️ 基于 Zynq-7 全可编程 SoC 的设计

sdk fpga zynq verilog xilinx vivado zynq-7010 zynq-7000 soc-fpga zynq-7020 soc-design

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HTML

RISMicroDevices / OpenNCB

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Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)

bus chisel chisel3 soc chi axi amba protocol-converter axi4 amba-axi soc-design amba-chi protocol-bridge

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Scala

williaml33moore / bathtub

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BDD Gherkin implementation in native SystemVerilog, based on UVM.

asic fpga bdd bdd-specs rtl verilog systemverilog uvm verilog-hdl bdd-framework asic-verification design-verification asic-design rtl-design soc-design soc-verification uvm-verification

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SystemVerilog

Vor-Art / DCD_MultiBankMemory

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SystemVerilog implementation of a multi-bank memory as part of "[F23] Digital Circuit Design" course

fpga throughput systemverilog innopolis-university soc-design multibank-memory

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SystemVerilog

iamstan13y / fomalhaut-microservices

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bootstrap docker redis mongodb postgresql web-api asp-net-core dapper grpc-service microservices-architecture solid-principles fluentvalidation rabbit-mq mediator-pattern razor-pages cqrs-pattern soc-design aggregator-services ocelot-api-gateway

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C#

Entries for the 2023 5th National College Student Integrated Circuit EDA Elite Challenge. SoC chip physical layout static IR drop prediction project based on methods such as image processing and NLP unsupervised learning.

machine-learning word2vec cnn power-network unsupervised-learning pix2pix vlsi-physical-design signoff u-net electronic-design-automation soc-design u-net-pytorch physical-layout-analysis ir-drop

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Python

amitops2103 / NASSCOM_VSD_SoC_Physical_Design_Program

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Digital VLSI Soc-Physical Design (Picorv32)

vlsi-physical-design soc-design physical-layout-analysis

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kichy-ge / openclaw-chip-agent-team

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A reusable OpenClaw agent squad for chip architecture, RTL, DV, STA, PD, DFT, analog, and layout collaboration.

dft verification multi-agent rtl ai-agents analog-design sta physical-design soc-design chip-design openclaw

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JavaScript

trustfarm / TFSDxr-Neuron-Quantization

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Humans respond more to **relative change (difference)** and **events (extrema/saturation)** than absolute levels. TFSDxr‑Neuron‑Quantization [TimeFeedBackSigmaDelta 4 eXtensible Reality] maps this principle into digital logic for **low‑power, event‑based encoding**.

ai scalable fpga codec neuron quantization neuromorphic gemm scalable-machine-learning soc-design

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soct-org / SoCeteer

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SoCeteer - A framework for designing and running RISC-V-based SoCs on FPGA and in Simulation, built on top of Chisel.

chisel risc-v xilinx-vivado verilator soc-design

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C

rehanmq / asic-soc-ml-accelerator-verification

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End-to-end ASIC SoC design and functional verification of a lightweight machine learning accelerator using SystemVerilog and UVM. Includes Python automation for test generation and result analysis. Built to simulate real-world ML silicon validation at scale.

systemverilog msp432 system-design verilator asic-verification soc-design ai-hardware

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Verilog

Free-95 / Plug-and-Play-IPs-for-any-SoC

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Open-source framework providing standardized, plug-and-play hardware IP blocks for System-on-Chip design. Includes a complete reference RISC-V SoC implementation, software drivers, and comprehensive integration documentation for FPGA deployment.

gpio fpga rtl verilog pwm risc-v soc-design ip-cores