static-timing-analysis

A High-performance Timing Analysis Tool for VLSI Systems

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• Verilog

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A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

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• C++

5 Day TCL begginer to advanced training workshop by VSD

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• Verilog

TCL Script automating the frontend of ASIC design

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• Verilog

UPSET is an automated framework for performing Single Event Transient Analysis and Optimisation for VLSI circuits utilising Static Timing Analysis principles. Documentation at:

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• Verilog

This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

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• Verilog

Incremental k-Critical Path Generation

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• C++

A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)

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• HTML

CAD in NYCU

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• Verilog

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• Verilog

An open-source tool for visualizing and analyzing timing paths extracted from Static Timing Analysis (STA) reports.

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• HTML

Microprocessor Design using Verilog HDL built and tested in Vivado Design Suite

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• Verilog

Full RTL-to-GDSII implementation of a 32-bit RISC Processor. Features Physical Design (P&R), CTS, and Timing Closure using Synopsys DC & Cadence Innovus.

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TCL Script to automate the generation of Pre-layout QoR results

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• Verilog

This repo implements VLSI static timing analysis using C++.

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• C++

This project is the script for STA report violated path checks temporarily (not final version due to confidentiality).

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• C

Adaptive Quadrant (AQ) reconfigurable 16-bit multiplier using quadrant decomposition and row bypassing for low-power operation. Implemented in RCA and hybrid prefix adder variants across TSMC 180nm/90nm using Cadence tools. Achieves significant power and area reduction with scalable architecture. SCI journal manuscript under review.

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Vending Machine Design using Verilog HDL built and tested in Vivado Design Suite

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• Verilog

NYCU 2025 Fall Special Topics in Computer Aided Design 陽明交大 劉建男 計算機輔助設計特論

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• Python