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datapath-design

Here are 18 public repositories matching this topic...

Awais-Asghar / 5-Stage-Pipelined-RISC-V-Processor-on-FPGA

A 5-Stage Pipelined RISC-V Processor designed and implemented on FPGA (Artix-7 Nexys A7). Supports RV32I instructions set (R, I, S, B, U, J types) with ALU, control unit, hazard detection, forwarding, and pipeline registers. Verified through simulation and hardware testing with optimized timing and 4× performance gain.

fpga processor systemverilog pipelining computer-architecture hazard-detection risc-v system-design riscv32 datapath-design pipelined-processor control-logic

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SystemVerilog

👁 RISC-Processor

Ecolash / RISC-Processor

𝗠𝗶𝗻𝗶𝗠𝗜𝗣𝗦 | 𝗥𝗜𝗦𝗖 𝗣𝗿𝗼𝗰𝗲𝘀𝘀𝗼𝗿 𝗗𝗲𝘀𝗶𝗴𝗻 | 𝗖𝗦𝟯𝟵𝟬𝟬𝟭 𝗖𝗼𝘂𝗿𝘀𝗲 𝗣𝗿𝗼𝗷𝗲𝗰𝘁

pipeline processor assembler vivado assembly-language-programming computer-architecture verilog-hdl instruction-set-architecture mips-architecture iitkgp control-unit fpga-programming controlpath computer-organization-and-design risc-architecture datapath-design

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Verilog

skipfie / CPEN211

CPEN 211: Introduction to Microcomputers 2022W1 with Prof. Lis

finite-state-machine ubc systemverilog university-course asic-design ubc-engineering datapath-design

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SystemVerilog

FarrukhAijaz / Single-Cycle-Multi-Cycle-and-Pipeline-ARM-Based-Processor-Design

Architecure for the Data path and Controller as well as Hazard Units for a 32 bit ARM based Single Cycle, Multi Cycle and Pipelined Based Processor

processor-architecture arm processor verilog mcu computer-architecture hazard-detection pipeline-processor verilog-hdl 32-bit arm32 pipline processor-design single-cycle-processor multi-cycle-processor multi-cycle-cpu datapath-design

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Verilog

shahed22 / Architectural-Design-for-Bus-interface-connected-with-LFSR

bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications

asic fsm interface architecture rtl verilog peripherals datapath soc testbench lfsr 32-bit 32bit bus-interface asic-design controlpath datapath-design lfsr-algorithm

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Verilog

sakethakella / ALU-Design

ALU Built with proper Datapath and Control path (FSM) to give appropriate results

fsm computer-architecture verilog-hdl vlsi-design datapath-design

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Verilog

mattiadane / Rock-Paper-Scissors-Circuit

University project about the game rock-paper-scissors

verilog sis datapath circuit systemverilog blif datapath-design fsm-designer

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SystemVerilog

DavideTenediniPoliMi / RL_Project_21_22

This was the project assignment for the Digital Logic Design course.

fpga vhdl digital-logic digital-logic-design convolutional-encoder datapath-design

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VHDL

Shameen-ghyas / MCDP-

This repository contains my Multi-Cycle Datapath (MCDP) project designed in Logisim for my Computer Organization and Design CEP. It’s a custom processor architecture built from basic components, executing each instruction over multiple clock cycles through distinct stages.

processor-architecture datapath-design

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RohithVeer / ARM32_BIT_CPU_DESIGN

Replicated and implemented a 32-bit ARM-style CPU in Verilog/SystemVerilog, covering full datapath, control logic, ALU, and memory integration, with functional verification through RTL simulation.

processor-architecture computer-architecture memory-systems datapath-design control-logic rtl-hardware-design alu-arithematic-logic

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SystemVerilog

Aledpl5 / Rock-Paper-Scissors-Circuit

Uni project about the game rock-paper-scissors

verilog sis datapath circuit systemverilog blif finate-state-machine datapath-design

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SystemVerilog

VLSI-Shubh / GCD-Calculator

Greatest Common Divisor calculator showcasing CPU-like controller + datapath architecture using subtraction-based Euclidean algorithm. Demonstrates synthesizable FSM design vs behavioral modeling trade-offs with complete hardware implementation.

controller verilog finite-state-machine euclidean-algorithm cpu-architecture datapath-design

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Verilog

gautamop01 / CS211-Computer-Architecture

Learned as a part of Computer architecture Course

computer-science architecture mips-assembly verilog vivado datapath alu mips-architecture mips-processor qtspim cs211 computerarchitecture asembly flowcontrol dynamicmemory datapath-design datapath-analysis

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Assembly

👁 LC2222a-ISA

tianrui-qi / LC2222a-ISA

Datapath and Control for a Turing Complete ISA with Interrupt Handling

microcontroller cpu networking system instructions logic isa datapath circuit interrupts lc-2200 datapath-design

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Assembly

canmayda17 / SingleCycleDatapath

Single Cycle MIPS Datapath implementation in Verilog that extends the standard MIPS architecture with seven custom instructions, featuring a complete processor design with control unit, ALU, register file, and memory components.

processor verilog computer-architecture instruction-set-architecture mips-architecture control-unit datapath-design

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Verilog

yanocavalcante / CTD-Jogo

Repositório para o trabalho final da disciplina de Circuitos e Técnicas Digitais do Prof. Héctor Pettenghi Roldán.

fpga vhdl datapath-design

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VHDL

ViniMF13 / Laboratorio_Sistemas_Digitais

Implementação do Projeto Final da Disciplina de Sistemas Digitais, oferecia pelo Departamento de Engenharia Elétrica da UFMG. O Projeto elabora um sistema de cofre digital, seguindo a metodologia de Resgister Transfer Level.

vhdl finite-state-machine rtl-design datapath-design

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VHDL

Shameen-ghyas / MIPS-Datapath

A simulated MIPS single-cycle datapath implemented in Logisim.

assembly-language datapath-design

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