single-cycle-processor

Single-Cycle RISC-V Processor using SystemVerilog on a Nexys A7 (Artix-7) FPGA. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. It supports the complete RV32I instruction set (R, I, S, B, U, J types).

fpga vivado computer-architecture system-verilog risc-v cpu-architecture processor-design single-cycle-processor digital-design-and-computer-organization rv32i-processor

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SystemVerilog

explcre / 21Summer-VE370-Intro-to-Computer-Organization-Projects

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21Summer-VE370-Intro-to-Computer-Organization-Projects: -Project1: RISC-V Assembly, simluating c code. -Project2: 1.RISC-V64 single cycle processor. 2.RISC-V64 five-stage pipelined processor. -Project3: Virtual memory, TLB, cache, memory simulator. -Project4: Literature review on Computer Organization.

cpu virtual-memory tlb risc-v cpu-emulator computer-organization tlb-simulator riscv64 computer-organisation-architechure risc-v-assembly single-cycle-processor 5-stage-pipeline computer-organization-lab computer-organization-and-design

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Verilog

Elzawawy / mips-processor-simulator

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A simplified MIPS machine simulator using SystemVerilog, developed with three different micro-architectures: single-cycle, multi-cycle and pipelined.

mips mips-architecture mips-simulator pipelined-processors single-cycle-processor multi-cycle-processor

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SystemVerilog

SnrNotHere16 / RISCVSingleCycleProcessor

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A RISC-V Single Cycle Processor which is done in verilog.

module verilog vivado computer-architecture risc-v 32-bit hardware-description-language riscv32 risc-architecture-processor single-cycle-processor testbench-generator-verilog

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Verilog

arhamhashmi01 / RV32I_Single_Cycle

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This repository contains the implementation of single cycle processor based on RISC-V ISA and implemented on "LOGISIM".

vhdl verilog microprocessor hardware-designs computer-architecture pipeline-processor rv32i single-cycle-processor 5-stage-pipeline 3-stagepipeline fetch-stage-pipeline

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Verilog

👁 ALEPH

samadpls / ALEPH

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Aleph is a single cycle processor that carries out one instruction in a single clock cycle

scala riscv chisel3 risc-v single-cycle-processor

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Scala

Vedant2311 / Complete-ARM-CPU

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Single and Multi-cycle ARM processors implemented using VHDL

fpga-programming single-cycle-processor multi-cycle-processor pmod-kypd multi-cycle-cpu

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VHDL

arsalanjabbari / MIPS-CPU-Design

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This project involves the creation of a single-cycle MIPS CPU design using Verilog. The single-cycle microarchitecture is characterized by executing an entire instruction in one clock cycle. The project delves into the intricacies of designing and implementing a simplified MIPS CPU, providing insights into its fundamental components.

mips cpu-design single-cycle-processor

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Verilog

Prajjv / RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg

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Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..

verilog microprocessor vivado fibonacci-numbers 7-segment risc-v fibonacci-sequence basys3 vivado-hls artix-7 basys3-fpga single-cycle-processor basys3-fpga-board

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Tcl

ArjunPShetty / Single_Cycle_RISC-V

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This project implements a RISC-V Single-Cycle processor in Verilog, integrating PC, ALU, register file, control, and memory into a simple reference CPU design.

cpu waveform rtl verilog testbench risc-v single-cycle-processor

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Verilog

OmarAmer01 / VP_Harvard_MIPS

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A 32-bit microprocessor with 42 instructions (including multiplication and division) and 8 X 32 registers and 2048 X 32 Ram with shared stack. An assembler is also available to write programs on the microprocessor using 8086-like assembly.

mips verilog computer-architecture vlsi modelsim single-cycle-processor