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URL: https://github.com/topics/instruction-level-parallelism

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instruction-level-parallelism

Here are 12 public repositories matching this topic...

sdasgup3 / parallel-processor-design

Super scalar Processor design

processor-architecture bison flex processor assembler parallel-computing verilog forwarding bypassing pipeline-processor superscalar opcode verilog-hdl instruction-set-architecture instruction-set processor-simulator branch-prediction pipeline-cpu mnemonics instruction-level-parallelism

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Verilog

dominiksalvet / super-riscv

Superscalar dual-issue RISC-V processor

open-source pipeline core rtl forwarding systemverilog gtkwave testbench superscalar in-order risc-v microarchitecture low-power verilator ahb3-lite instruction-level-parallelism dual-issue riscv-gcc

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SystemVerilog

SIMDE-ULL / SIMDE

Educational computer simulator on a mission to "superscale" the study of computer architecture fundamentals

simulator educational learning-by-doing pipelining computer-architecture risc out-of-order superscalar learning-resources instruction-level-parallelism computer-architecture-and-organization

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TypeScript

w-feng / CompArch-MIPS-POWER

Curriculum material for teaching computer architecture with MIPS and POWER

cpu memory gpu architecture pedagogy computer-architecture computer-organization instruction-level-parallelism thread-level-parallelism data-level-parallelism

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Python

CSpyridakis / Tomasulo

Introduction in Dynamic Instruction Scheduling (Advanced Computer Architecture) implementing Tomasulo's Algorithm

pipeline architecture vhdl computer-architecture pipeline-processor out-of-order tomasulo instruction-level-parallelism tomasulo-algorithm

Updated
VHDL

IAA03 / IAA03-fast-atan2

IAA03_fast_math is a single-header math kernel(Atan2 only for now) designed to eliminate the "Trigonometry Tax" in high-throughput systems (Physics Engines, Audio DSP, and ML Pre-processing). Branchless ,ILP and SIMD (AVX2/SSE4.1), it achieves up to a ~186x per-element throughput speedup over std::atan2 while being IEEE 754 compliant

cpp robotics high-performance simd high-performance-computing low-latency sse41 atan2 instruction-level-parallelism avx-512 fast-math avx2-optimized

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C++

gocho1307 / Labs-OC

Project for 2023/2024 - Computer Organization @ IST

cache university-project pipelining instruction-level-parallelism

Updated
C

sebastian-wardzinski / computer-architecture

ECE552: Computer Architecture — Fall 2020.

multithreading computer-architecture branch-prediction cache-coherence cache-optimization instruction-level-parallelism memory-consistency dynamic-scheduling control-hazards data-hazards multiprocessor-systems superscalar-cpu

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C

LucasBarros28 / tomasulo-algorithm

Simulação ciclo-a-ciclo do algoritmo de Tomasulo em C++, com suporte a estações de reserva, ROB e Common Data Bus.

simulator cpp instruction-level-parallelism tomasulo-algorithm dynamic-scheduling

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C++

sid-xyz / RNBIP_Pipelined-Microprocessor

Redesigned the RNBIP single-bus architecture to implement a 3 stage instruction-level pipeline.

fpga architecture microprocessor academic-project instruction-set-architecture instruction-level-parallelism

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Verilog

scicomp-durham / comp3577-mimd-code

Examples of OpenMP for instruction-level parallelism.

openmp instruction-level-parallelism mimd

Updated
C

K-Wu / intrasm_engine

Enhancing CUDA Intra-Streaming-Multiprocessor Parallelism for Large Language Models via Fine-Grained Task Graph

pytorch transformer sparse-matrix cupy peft instruction-level-parallelism llm cuda-graph

Updated
Jupyter Notebook

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