memory-design

Design of 6T, 8T and 10T SRAM Cells with Static Noise Margin Analysis

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• AGS Script

Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations

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• SourcePawn

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• C#

This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.

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• Verilog

Design and analysis of a 7T SRAM cell using Cadence Virtuoso in 90 nm CMOS technology.

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This repository contains a Verilog-based design and testbench for modeling a simple asynchronous RAM module. It is designed to simulate basic memory read/write behavior without the use of a clock, allowing learners and engineers to better understand low-level memory interactions.

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• Verilog

Behavioral architecture of a read/write cycle controller for a DRAM chip.

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• VHDL

PESU Sem 3: Mini project for Digital Design and Computer Organization

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• Verilog

DRAM/SRAM 반도체 메모리 설계·시뮬레이션·검증 엔진 — RC 방전·Arrhenius·SNM·Row Hammer·센스앰프 BER (순수 Python)

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• Python

Repository with shell scripts, OS installation tasks, assembly language, and HDL files for the Computer Architecture and Operating Systems (ACSO) course at Escuela Colombiana de Ingeniería.

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• Assembly

Complete 64-bit 6T SRAM array with custom peripheral circuits in 120nm PDK. Achieved 3× FOM improvement through VDD/2 precharge and OTA-based sense amplifiers.

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SRAM Collection – Parameterized Verilog Modules for Single Port SRAM (sync/async read), Pseudo Dual Port SRAM (sync read), and True Dual Port SRAM – all parameterized, fully synthesizable, and demo’d with testbenches and waveforms.

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• Verilog