Opensource DDR3 Controller
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- Verilog
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memory-controller
Here are 17 public repositories matching this topic...
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
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- Verilog
mirror of https://git.elphel.com/Elphel/eddr3
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- Verilog
This is not Linux kernel maintainer's tree, but an open-source work in progress. Officially maintained repositories are under kernel.org (Samsung SoC, memory controller drivers etc.).
linux arm kernel linux-kernel tesla armv7 samsung odroid arm64 devicetree snapdragon qualcomm armv8 exynos fsd qcom memory-controller samsung-soc gs101 gs201
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- C
A bare-metal SRAM memory controller suitable for Xilinx FPGAs.
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- Verilog
Multi-Channel DDR Memory Controller Design with BFM-Based Verification and UVM-Style Testbench
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- Verilog
🛠 A SDRAM controller in Verilog HDL
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- Verilog
This repository contains a JEDEC-style DDR2 SDRAM controller targeting the memory devices. The controller exposes a simple FIFO-like front-end interface and maps host commands into DDR2 transactions, including full power-up initialization, periodic refresh, scalar and block reads/writes, and DQS-based data capture.
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- SystemVerilog
The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.
memory verilog sram memory-management vivado questasim sdram sdram-controller memory-controller verilog-project vlsi-design sram-controller sram-controller-advanced sram-features-power-security-brust verlog-hdl enhanched-sram-controller
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- Verilog
Behavioral architecture of a read/write cycle controller for a DRAM chip.
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- VHDL
This repository contains a JEDEC-style DDR2 SDRAM controller targeting the memory devices. The controller exposes a simple FIFO-like front-end interface and maps host commands into DDR2 transactions, including full power-up initialization, periodic refresh, scalar and block reads/writes, and DQS-based data capture.
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- Verilog
DDR memory controller implementation and verification
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Advanced SRAM Controller with ECC Support for Sky130 Process - Production-Ready Multi-Port Memory System.
fpga verification pytest systemverilog open-source-hardware cocotb memory-controller vlsi-design sram-controller asic-design ecc-memory sky130 multi-port-memory
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- Python
Redesign of 'vga_src' video card architcture using proper FIFOs
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- Verilog
In this repository, I have published my knowledge gained while working on FIFO Project implementation using Verilog, System Verilog, UVM
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- SystemVerilog
This project is a course based see SEC/term 7/Computer Architecture
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- Verilog
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