Skip to content
You signed in with another tab or window. to refresh your session.
You signed out in another tab or window. to refresh your session.
You switched accounts on another tab or window. to refresh your session.
Here are
22 public repositories
matching this topic...
👁 fomu-workshop
Support files for participating in a Fomu workshop
FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
AXI support for Migen/MiSoC
Open source Logic Analyzer based on LiteX SoC
Template project for LiteX-based SoCs
gateware for the main fpga, including a hispi decoder and image processing
USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface
Describing RTL circuit in Ruby
Scripts and gateware for the TinyFPGA bx
Gateware and software for Fastino (32 channel 2.5 MS/s 16 bit DAC for the Sinara ecosystem)
CPLD gateware for the Sinara Urukul module
WARC Open Fusesoc Cores Repository
Hardware Motion and Motor Control Library
A unit-test framework for testing Migen modules directely on hardware.
A Python toolbox for building complex digital hardware [fork for adding nexsys3 support]
CPLD gateware for the Sinara Mirny module.
Improve this page
Add a description, image, and links to the
migen
topic page so that developers can more easily learn about it.
Curate this topic
Add this topic to your repo
To associate your repository with the
migen
topic, visit your repo's landing page and select "manage topics."
Learn more
You can’t perform that action at this time.
