vivado-vitis

Here are 11 public repositories matching this topic...

victorricardoaguilerasanchez / EclypseZ7_DIAL_System

This repository include all the codes and constraints used in the development of the Master Thesis: "Development of a Differential Absorption Lidar System based on a SoC-FPGA for Carbon Dioxide Sensing" by Victor Ricardo Aguilera Sanchez

pic lidar cross-correlation lfsr prbs-generator baremetal-programming eclypse-z7 zmod co2-sensing dial-system m-sequence vivado-vitis zmod-modules adc-dac oscilloscope-awg rm-cw

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aryan-programmer / axi_gen_and_sum_primes_fpga

Star

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls axi-memory-mapped

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TeX

ShouryaSaklecha / FPGA_Audio_Networking

Star

A real-time audio streaming platform utilising FPGAs and Ethernet

vhdl xilinx ethernet kv260 vivado-vitis

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C

aryan-programmer / axi_stream_array_sum_microblaze

Star

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.

embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado microblaze axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls

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C

der-mur / zynq-cpp-sandbox

Star

This is my sandbox for exploring the use of C++ to develop projects for the AMD (Xilinx) Zynq. One of the aims is to begin the process of creating a range of c++ drivers that can be re-used for other Zynq-7000/Ultrascale/Microblaze designs. The IDE is Vivado/Vitis 2023.2 (Classic version).

cpp vivado zynq-7000 vivado-vitis digilent-zybo-z7-20

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HTML

EMBKSM / Z-Modem

Star

FPGA-based Real-time QPSK Image Transceiver

fpga csharp winforms aes-128 systemverilog verilog-hdl qpsk-modulation vivado-vitis

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Verilog

ananyakarra / MIPS32-Pipelined-Processor

Star

High-level block designs for MIPS 32 bit processor with pipelining & forwarding controls, hazard detection, and timing. Tested and verified in course on organization of computers.

verilog mips32 pipelined-processors vivado-vitis pipelined-memory

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Verilog

hen-er / Summer24-Hardware-Acceleration-Research

Star

Exploring the possibility of developing customized hardware solutions (i.e. FPGA deployment) for a time-intensive iterative matrix transformation procedure. Them initial stages involve skill building and developing experience through isolated tests using HDLs, HLS, and FPGAs.

fpga verilog vivado systemverilog high-level-synthesis c-programming-language vivado-vitis

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SystemVerilog

dennisleexyz / vitis-2019.2

Sponsor

Star

(Arch Linux package) Xilinx FPGA/CPLD design suite downgraded to version 2019.2

fpga aur archlinux arch arch-linux xilinx vivado aur-packages xilinx-fpga xilinx-vivado fpga-programming vitis vivado-installer xilinx-vitis vivado-vitis

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Shell

dan-lara / Spectrum-Analyzer

Star

This project aims to develop a spectrum analyzer system using the Zynq-7000 board. The system will capture audio input (I2S), process it through a well-defined internal architecture, and output the data via DMA to a VGA screen. The VGA screen will display the signal as a frequency spectrum using FFT (Fast Fourier Transform).

vivado zynq-7000 i2s-audio vdhl vivado-vitis

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C

cztee / EBAZ4205_SelfStudy_Notes

Star

fpga-programming ebaz4205 vivado-vitis

Updated

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vivado-vitis

Here are 11 public repositories matching this topic...

victorricardoaguilerasanchez / EclypseZ7_DIAL_System

aryan-programmer / axi_gen_and_sum_primes_fpga

ShouryaSaklecha / FPGA_Audio_Networking

aryan-programmer / axi_stream_array_sum_microblaze

der-mur / zynq-cpp-sandbox

EMBKSM / Z-Modem

ananyakarra / MIPS32-Pipelined-Processor

hen-er / Summer24-Hardware-Acceleration-Research

dennisleexyz / vitis-2019.2

dan-lara / Spectrum-Analyzer

cztee / EBAZ4205_SelfStudy_Notes

Improve this page

Add this topic to your repo