A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.
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vitis-hls
Here are 50 public repositories matching this topic...
LLM-Aided FPGA Design for Signal Processing Applications
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- C++
Advanced multi-band GNSS SDR front-end implementation in an RFSoC integrated circuit. GPL-3.0 license
python c-plus-plus front-end signal-processing sdr vivado gnss rfsoc vitis-hls multi-band direct-rf-sampling
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- Jupyter Notebook
DaCH: dataflow cache for high-level synthesis.
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LLM-Aided FPGA Design Optimization
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FPGA Acceleration for the LoFreq variant caller
bioinformatics fpga hls probability-distribution xilinx variant-calling bioinformatics-tool lofreq vitis-hls poisson-binomial-distribution counting-models
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Flexible Linear Algebra with Matrix-Empowered Synthesis (for Vitis HLS)
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Xilinx Tools Tutorials
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- Jupyter Notebook
Vitis (Vivado) HLS Examples
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Deep Learning Aided Radar Signal Processing on Zynq SoCs for Doppler Estimation with hardware (Zynq SoC IPs)
music zynq driver jupyter-notebook dnn neural-networks vivado root-music esprit vivado-hls pynq-z2 vitis zcu111 vitis-hls
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- VHDL
FPGA SpMV (CSR/ELL/COO) with Vitis HLS + Vivado on HyperFPGA. Includes HLS IP, block designs, and host scripts. Replicate any method via SpMV_FinalSourceFiles.
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- Jupyter Notebook
Hardware-accelerated CNN on Xilinx Zynq-7020 FPGA for real-time Person/Object detection. Built with Vitis HLS, Vivado & PYNQ — no Vitis AI, no FINN.
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- Verilog
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls axi-memory-mapped
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- TeX
Accelerated Stencil Computation with Optimized Dataflow Architecture on FPGAs
fpga hls accelerator architecture vlsi high-level-synthesis stencils vivado-hls stencil-computations vitis-hls
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Work on your Vitis HLS project from within VS Code
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- TypeScript
An accelerated implementation of the kNN algorithm on the Kria KV260 FPGA
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- C++
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